Method of forming an implantable electronic device chip level hermetic and biocompatible electronics package using SOI wafers

ABSTRACT

The invention is directed to a hermetically packaged and implantable integrated circuit for electronics that is made my producing streets in silicon-on-insulator chips that are subsequently coated with a selected electrically insulating thin film prior to completing the dicing process to yield an individual chip. A thin-layered circuit may transmit light, allowing a photodetector to respond to transmitted light to stimulate a retina, for example. Discrete electronic components may be placed in the three-dimensional street area of the integrated circuit package, yielding a completely integrated hermetic package that is implantable in living tissue.

CROSS REFERENCE TO RELATED APPLICATION

This application is a divisional of U.S. application Ser. No.10/360,988, “Chip Level Hermetic and Biocompatible Electronics PackageUsing SOI Wafers”, filed Feb. 7, 2003, the disclosure of which isincorporated herein by reference, which claims the benefit of U.S.Provisional Application No. 60/440,806, “Chip Level Hermetic andBiocompatible Electronics Package Using SOI Wafers”, filed Jan. 17,2003, the disclosure of which is incorporated herein by reference.

FIELD OF THE INVENTION

This invention relates to a hermetic integrated circuit and a method ofmaking an integrated electronic circuit by utilizingsilicon-on-insulator (SOI) techniques.

BACKGROUND OF THE INVENTION

This invention relates to electrically insulating thin film processesthat are hermetic and that are used to encapsulate integrated circuits(ICs) for the purpose of forming a protective package for an electroniccircuit, where the ICs are applicable to devices that are implanted inliving tissue, such as neural prostheses or retinal electrode arrays.The package may have electrical feedthroughs to connect electrically tothe outside environment. The electric circuit may interface with theoutside environment optically (for example, infrared or laser) or viaelectromagnetic means, such as radio frequency (RF) and thus it may notneed an exposed feedthrough. Additionally, the hermetic film may be madeselectively electrically conductive in certain regions to facilitatesignal transmission or power transmission.

The main drawback to thin film packaging of electronic circuits that areimplanted in living tissue is that the process is typicallythree-dimensional since the entire IC needs to be packaged (encapsulatedin a thin film). This results in long deposition times that add cost andthat could exceed the thermal budget of the electronic circuits, therebydestroying the device. The invention describes a device and means forreducing the required deposition process time by allowing an equivalentpackage to be constructed in a two-dimensional deposition that coversseveral chips at the same time at the wafer level.

SUMMARY OF THE INVENTION

In accordance with a preferred embodiment of this invention, theapparatus of the instant invention is a hermetic and biocompatibleelectronics package that is made by applying silicon-on-insulator (SOI)technology and thin film deposition technology to enable large-scaleproduction of individual integrated circuits for electronic packagesthat may be implantable in living tissue.

The SOI wafer is diced partially through its thickness. The spacesbetween the chips, die, or reticules are scored or semi-diced by one ofseveral known means, in order to produce three-dimensional streets. Thedepth of these three-dimensional streets passes completely through thesilicon layer and partially through the insulating layer. Thethree-dimensional streets are then coated along with the silicon layerto yield a hermetic electronics package that is suitable forimplantation in living tissue.

In accordance with an alternative embodiment, the thin silicon layer maybe transparent to light, thus allowing light to strike a photodetectoron the surface away from the light source. This may have application inneural prostheses or retinal electrode arrays, for example, where lightpasses through the integrated circuit, strikes a photodetector, which inturn stimulates the retina to enable vision in a non-functioning eye. Inthis case, it passes through the insulator then through thesilicon/integrated circuit layer.

A further embodiment places discrete electronic circuit components inthe street area of the integrated circuit. The discrete component isthen coated and thus part of the hermetically sealed, implantableelectronics package.

The novel features of the invention are set forth with particularity inthe appended claims. The invention will be best understood from thefollowing description when read in conjunction with the accompanyingdrawings.

OBJECTS OF THE INVENTION

It is an object of the invention to produce a hermetically sealedintegrated circuit using silicon-on-insulator technology and thin filmdeposition technology.

It is an object of the invention to produce a light transparentthin-layered integrated circuit chip using silicon-on-insulatortechniques.

It is an object of the invention to produce a discrete integratedcircuit that has discrete electronic components hermetically protectedwherein select components are located in the street area of theintegrated circuit.

Other objects, advantages and novel features of the present inventionwill become apparent from the following detailed description of theinvention when considered in conjunction with the accompanying drawing.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a cross sectional side view of thesilicon-on-insulator chip assembly.

FIG. 2 depicts a cross sectional side view of the silicon-on-insulatorchip assembly showing the insulating thin film.

FIG. 3 depicts a cross sectional side view of a singlesilicon-on-insulator chip.

FIG. 4 illustrates a cross-sectional side view of a light transparentinsulator with a photoelectric cell.

FIG. 5 depicts a hermetically coated silicon-on-insulator IC with adiscrete component.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Starting with a base substrate wafer facilitates reducing process time.A silicon-on-insulator (SOI) wafer is used as the starting substrate asopposed to a standard silicon wafer. The invention is not limited to asilicon wafer, and it is envisioned that alternative semiconductors maybe employed, such as gallium arsenide. In the case, where the integratedcircuit (IC) is suitable for implantation in living tissue, asilicon-on-sapphire (SOS) or a silicon-on-diamond (SOD) wafer formsalternate embodiments, because the insulating layer is bothbiocompatible and bio-inert. A preferred embodiment is to the broaderclass of SOI wafers for electronic circuits for forming ICs forelectronic circuits.

Using these wafers, the circuitry is designed using an electronicsprocess that is known to one skilled in the art (e.g., 0.5 um CMOS) andthis process is conducted to produce a wafer of functional die, such asICs or chips). Typically, such wafers are post-processed, such as beingthinned and polished, then diced into individual chips that are placedinto their own packages. In a preferred embodiment, a wafer 2 is dicedpart of the way through, such that the spaces between the chips, die, orreticules are semi-diced by one of several known means in order toproduce a three-dimensional street 8 having a depth that passescompletely through a silicon layer 6 and partially through an insulatorsubstrate 4, as shown in FIG. 1.

The insulator substrate 4 is preferably comprised of silica, although inalternative embodiments it may be comprised of glass or oxide materialsthat are electrical insulators. For implantation in living tissue, theinsulator substrate 4 is preferably selected from a group of materialsthat are biocompatible and bio-inert, such as sapphire, diamond, silica,or oxide ceramics.

The main advantage of such a technique is that it eliminates the need tocover the back of the ICs with an electrically insulating and hermeticthin film, while permitting a single coating deposition process at thewafer level. The wafer level deposition of the insulating thin film 10covers the sides of the three-dimensional street 8, eliminating the needfor any further deposition coatings. Choices for the deposition processfor the insulating thin film 10 and material selection are known in theart. Candidate materials include diamond, such as ultra-nanocrystallinediamond (UNCD) or ceramics, such as alumina.

The thin film process is preferably a physical vapor deposition such asIon Beam Assisted Deposition (IBAD), which like physical vapordeposition processes, is line-of-sight deposition, it none the less iscapable of uniformly covering high aspect ratio features. In analternative embodiment, a CVD process (which is not line of sight), suchas microwave plasma chemical vapor deposition (MPCVD), is selectedbecause it is also well suited to this requirement as it naturally fillsin regions such as the three-dimensional street 8. After a blanketdeposition of the insulating thin film 10 over the entire wafer (whichmay be accomplished in several layers) the resulting structure appearsas presented in FIG. 2.

A further alternative embodiment utilizes an IC package that is at leastpartially transparent to light 14, as illustrated in FIG. 4, where thelight 14 is preferably visible light. In alternative embodiments, thelight 14 may include other types of electromagnetic radiation that isdetectable with a sensor that is specific to the transmitted radiation.By using an SOI device, the insulator 12 may be chosen to have favorabletransmission properties for electromagnetic radiation 14. A preferredembodiment has a photoelectric cell 16, which includes, but is notlimited to, photo detectors, cadmium sulfide crystals, light sensors,phototransistors, or photodiodes that are located on a surface away fromthe light source.

In alternative embodiments, the photoelectric cell 16 may be anyelectronic circuit that responds to exposure to electromagneticradiation 14 by generating an electric impulse. In FIG. 4, thephotoelectric cell 16 is located in the silicon layer 6 and is separatedfrom the transparent insulator 12 by a portion of the silicon layer 6.The invention is not limited to silicon layer 6 and it is envisionedthat alternative semiconductor materials may be employed, such asgallium arsenide. In alternative embodiments, the photoelectric cell 16is in direct contact with transparent insulator 12. The photoelectriccell 16 may be located on the surface of the insulator 12, in analternative embodiment.

A preferred application is a device such as a neural prosthesis wherethe prosthesis may alternately be a retinal electrode array ordemultiplexer, wherein the transmitted light 14 stimulates aphotoelectric cell 16, which in turn stimulates the retina, enabling anon-functioning eye to detect and see visible light. Alternativeembodiments enable other types of electromagnetic radiation 14, such asinfrared or ultraviolet radiation, to be detected after the radiationpasses through the transparent insulator 4.

In yet another embodiment, FIG. 5, a discrete electronic component 20 isplaced in a hole 24 that passes part of the way through the thickness ofinsulator substrate 4. The hole 24 is formed by any of the techniquesthat are know in the art, such as reactive ion etching, laser ablation,wet etching, dry etching, or combinations of these techniques. The hole24 is filled with an electrically insulating fill 22, preferably epoxy.After final dicing into a packaged chip, the discrete component 20 ishermetically protected in the three-dimensional street 8 of thehermetically packaged and implantable IC, having been covered with theelectrically insulating thin film 10. In a preferred embodiment, thediscrete component 20 is a capacitor, although in alternativeembodiments the discrete component 20 may be a resistor, filter,inductor, or a combination of these electronic circuitry elements.

The advantages of this packaging approach for an implantable IC chip isthat all electronic circuitry is in a single package with internalelectrical leads that are hermetically sealed in the package, therebyeliminating the need for external connections and feedthroughs, whichare notoriously difficult to hermetically seal for long-term livingtissue implant applications.

The chips can be singulated completely by a second dicing cut in thepreviously formed three-dimensional street 8 using known techniques,such as laser cutting, standard dicing, or a similar procedure. Theresulting packaged chip is depicted in FIG. 3.

Using the disclosed techniques, a wafer that contains numerous discretechips, perhaps hundreds of discrete chips, is packaged in a fraction ofthe time that it previously took to package just one chip.

Obviously, many modifications and variations of the present inventionare possible in light of the above teachings. It is therefore to beunderstood that, within the scope of the appended claims, the inventionmay be practiced otherwise than as specifically described.

1. A method of forming an implantable electronic device, comprising thesteps of: selecting a silicon-on-insulator chip assembly that comprisesa silicon layer and an insulator substrate that has a thickness, saidsilicon layer bonded to said insulator substrate; making a street thatpasses through said silicon layer and that passes partially through saidthickness of said insulator substrate; coating said silicon layer andsaid street with a coating; and extending said street through saidthickness of said insulator substrate.
 2. The method according to claim1, further comprising the steps of: selecting said insulator substratethat is transparent to electromagnetic radiation; and mounting at leastone photoelectric cell on said insulator substrate to detect saidelectromagnetic radiation.
 3. The method according to claim 1, furthercomprising the steps of: selecting a discrete electronic component; andembedding said discrete electronic component in said insulatorsubstrate.
 4. The method according to claim 1, further comprising thesteps of: selecting said coating from the group consisting of diamond,ultra-nanocrystalline diamond, ceramics, or alumina; and depositing saidcoating by ion beam assisted deposition.
 5. The method according toclaim 1 wherein said silicon layer comprises an integrated circuit. 6.The method according to claim 1 wherein said insulator substrate has anexposed area of said insulator substrate that is covered by saidhermetic electrically insulating thin film.
 7. The method according toclaim 1 wherein said hermetic electrically insulating thin film iscomprised of alumina.
 8. The method according to claim 1 wherein saidhermetic electrically insulating thin film is comprised of diamond. 9.The method according to claim 1 wherein said hermetic electricallyinsulating thin film is biocompatible.
 10. The method according to claim1 wherein said at least one discrete electronic component is furthercomprised of a capacitor.
 11. The method according to claim 1 whereinsaid at least one discrete electronic component is embedded.
 12. Themethod according to claim 1 wherein said insulator substrate istransparent to light.
 13. The method according to claim 1 wherein saidsilicon layer contains at least one photoelectric cell that produces anelectric impulse when stimulated by electromagnetic radiation.
 14. Themethod according to claim 1 wherein said silicon layer contains at leastone photoelectric cell that produces an electric impulse when stimulatedby light.
 15. The method according to claim 1 wherein said insulatorsubstrate is glass.
 16. The method according to claim 1 wherein saidinsulator substrate is sapphire.
 17. The method according to claim 1wherein said electronics package comprises a neural prosthesis.